1. Field of the Invention
The present invention relates generally to semiconductor memory devices and more particularly to highly integrated dynamic random-access memory (DRAM) devices using metal oxide semiconductor (MOS) transistors.
2. Description of the Related Art
In the manufacture of a digital equipment such as a computer, MOS dynamic random access memory (DRAM) devices are more widely used as the speed and cost advantages of these devices increase. The cost per bit of storage using MOS DRAMs has gone down as the number of bits or memory cells per package goes up. Such high integration of DRAMs comes with the advanced semiconductor microfabrication technology that breaks through the conventional design limit of on-chip element size.
As the semiconductor DRAM devices require higher packing density, the bit number increases and the cell size decreases. Accordingly, the setting of drive voltages internally applied in DRAM devices becomes more critical. While the DRAMs conventionally use the external power supply voltage Vcc, the internal drive voltages should be suitably adjusted so as to ensure that the reliability is as high as required.
In the presently available "semiconductor systems" having one or a plurality of circuit boards on which a various types of semiconductor devices are arranged or mounted including DRAM devices, central-processing units (CPUs), gate-array logic circuits and so forth, their basic power supply scheme has been kept unchanged wherein a single power supply voltage Vcc of a predetermined fixed standard potential (typically, +5 volts) is externally supplied to external power supply terminals of them. Highly integrated DRAMs are provided with a on-chip voltage converting circuit for converting the power supply voltage Vcc into a potentially decreased "down-converted" voltage for use in the drive voltages to achieve a suitable adjustment of the internal drive voltages. Such a circuit is generally known as a "voltage-down conversion (VDC) circuit" in the art to which the present invention pertains. The VDC circuit receives the power supply voltage Vcc externally supplied thereto, and generates a specific internal voltage that is potentially less than voltage Vcc.
VDC-included DRAM devices are described, for example, in Journal of Solid-State Circuits (JSSC), vol. 23, No. 5 "A 16-Mbit DRAM with a Relaxed Sense-Amplifier-Pitch Open-Bit-Line Architecture" (October 1988) at pp. 1104 to 1112. Similar DRAMs are also described in (1) JSSC, vol. 23, No. 5, "A 60-ns 16-Mbit CMOS DRAM with a Transposed Date-Line Structure" (October 1988) at pp. 113 to 1119, (2) JSSC, Vol. 24, No. 3, "An Experimental 16-Mbit CMOS DRAM Chip with a 100-MHz Serial READ/WRITE Mode" (June, 1989), at pp. 763 to 770, etc. The DRAMs as taught by these documents employ various kind of VDC circuits, including a VDC circuit for supplying an internally down-converted lower voltage to a memory cell array section only, a VDC circuit for supplying such down-converted voltage not only to the memory cell array section but also to the remaining circuit sections of a DRAM including peripheral circuits, and a VDC circuit for generating two kinds of down-converted voltages lower than the power supply voltage Vcc, one of which is for the memory cell array section, and the other of which is for the peripheral circuits.
As generally known among those skilled in the art, in the MOS DRAM devices, a voltage applied to a memory cell section determines the level of a logic "1" write (program) at a selected memory cell. The logic "1" write level is potentially equivalent to the bit-line restore voltage. To charge a bit line having a relatively large load toward a target potential level during a desirably shortened time period, a bit-line drive circuit requires an electric power of enhanced current supplying ability. Such requirement will be stronger as the integration density increases to increase the total bit-line capacity being charged or discharged within one row address strobe (RAS) cycle. This may cause an alternate current (AC) potential fluctuation to take place in the down-converted voltage internally generated in a DRAM chip. The AC potential fluctuation leads to the occurrence of a noise. The amount of noise will be a serious bar to the maintenance of an enhanced reliability in an event that the charging load capacitance, which is increased as the DRAM devices are further improved in integration density in future, is charged up or "restored" at a higher speed in a shortened RAS cycle.
A MOS DRAM device containing a conventional VDC circuit is described, for example, in JSSC, Vol. 24, No. 5, "A 45-ns 16-Mbit DRAM with Triple-Well Structure," October, 1989 at pp. 1170 to 1175. A sense amplifier as disclosed in FIG. 10 of it includes a driver transistor, which is connected to an external power supply voltage Vext and a common source line SAP of a restoring P-channel MOS sense amplifier circuit. A voltage comparator circuit is coupled to the common source line SAP. Common source line SAP begins to be charged by the driver transistor toward power supply voltage Vext in synchronism with a sense amplifier activation signal SE. The potential on common source line SAP increases gradually. When the comparator detects that the common source potential reaches a predetermined restore potential being equal to the down-converted voltage, the driver transistor is forced to turn off. The bit-line restore operation is then terminated.
More specifically, a current Isap flowing in the common source line SAP rushes to flow into the bit-line load capacitance by way of the driver transistor in synchronism with the sense amplifier activation signal SE. As common source line SAP rises potentially, the gate-to-drain voltage of the driver transistor decreases; common source current Isap decreases gradually. When the voltage on common source line SAP is finally at the restore voltage, the comparator detects it, causing the driver transistor to cut off. Common source current Isap becomes zero. When this transistor is cut off, the time varying rate di/dt of current Isap becomes the greatest value. The DRAM has an inductance component L that is inherent in the lead frame or bonding wires of its chip. Accordingly, an AC noise will occur which is determined by the product of the time varying rate di/dt and the inductance L, which is represented by "L.multidot.di/dt." The occurrence of such AC noise is a serious bar to the attainment of an excellent operating reliability of the DRAM device.